According to design convention, memory devices, such as DRAMs and SDRAMs, include a double data rate (DDR) transfer capability. DDR uses both the leading and falling edges of a clock signal when transferring data during read and write operations. Operating a DDR typically adheres to standards set by JEDEC, once known as the Joint Electron Device Engineering Council. As defined by JEDEC standards, after the issuance of a read and/or write command, a data strobe (DQS) signal, generated by the memory for indicating the availability of data, changes to a logic low for a full clock period (tCK) preceding the transfer of data. It is commonly known as the DQS preamble and its associated tolerance ranges from 0.9 to 1.1 of the clock period. Thereafter, data is transferred with each rising and falling edge of the DQS signal.
In a memory module having multiple memory devices, each memory device has its own DQS line coupled to a controller. A timing problem can arise, however, when DQS signals between more than one memory device simultaneously compete for controlling data transfer on the data bus. In some instances this might even lead to a corruption in data transfer. To illustrate this problem, reference is taken to FIG. 1 where a timing diagram for a fourth to first socket read operation is presented (where the first socket is physically closest to the controller, the second socket is next closest, etc.). It will be appreciated that this problem applies equally to write operations although no explicit example is presented.
In FIG. 1, a clock signal, CK, and its inverse, CK#, provide synchronized clocking control in a memory module having at least four sockets capable of containing memory devices. The CK has six complete periods shown as T0 through the beginning of T7. Dashed lines are shown that correspond to one-half of a clock period. The fourth socket DQS signal corresponds to a read command (not shown) occurring at T0. The first socket DQS signal corresponds to a read command (not shown) occurring at T3. The data signals, DQ, for each read operation of the fourth and the first sockets correspond to a burst length of four data bits, D0, D1, D2 and D3 that are transferred on the data bus with each rising and falling edge of its corresponding DQS signal after the time period of its DQS preamble shown as tRPRE (“RPRE” meaning Read Preamble).
As shown, the time period of the DQS preamble for the 4th socket begins shortly after period T1 while for the 1st socket it begins shortly before T4. The DQS preambles do not both begin at precisely the same position relative to the clock periods due to the +/− time tolerances that can stack up between memory modules. Such tolerances are well known and include, for example, minimum and maximum times for low impedance (LZ), high impedance (HZ), access time (AC), etc. As such, the timing shown is merely illustrative.
Just after time T3n, the DQS signal for the 4th socket begins a transition from logic high to logic low to transfer the fourth and last data bit, D4, on DQ signal line. Midway between such transition, the DQS signal begins the read postamble period as shown by tRPST. The time difference between the beginning of tRPST for the 4th socket and the beginning of tRPRE for the 1st socket is shown diagrammatically in FIG. 1 as 0.5*tCK−tDQSCK(max)−tLZ(min). In this expression, tDQSCK(max) is the maximum time for an access window of DQS from a CK/CK# crossover, shown as a time difference between the crossing of CK/CK# and the center of the following transition in DQS from a low to a high. Also, tLZ(min) is the minimum time for data-out low-impedance window of DQ from a CK/CK# crossover, shown as a time difference between the beginning out of data and the following crossing of CK/CK#. It can be seen that the data transfers associated with the DQS signals for these two sockets do not conflict with one another.
As maximum time tolerances are added (stack up), and as the physical distance between sockets increases, there remains only a fixed amount of time before conflicts occur between the data transfers associated with different DQS preambles. For a conventional clock period, tCK, of 10 nsec, a memory module has a time margin to prevent conflicting data transfers, so long as the electrical line length (length of time for a signal to propagate between the fourth socket and the first socket) is less than the time margin. In one prior art memory module, the memory module has timing parameters providing a time margin of 3.538 nsec that is defined by the margin equation,margin=½tCK−tDQSCK(max)−tLZ(min)+½tT, ormargin=½tCK−Late−Early,and summarized by the following data in nsec:
TABLE 1Timing Margin for 4th to 1st Socket Readwith a 10 nsec clock, CK, periodclocktLZ(min)tDQSCK(max)½ tTmaxslewEarlyLatemargin100.80.80.1380.80.6623.538where ½tT=½tTmaxslew is one-half of the time to completely transition a signal from a logic high to a logic low, or vice versa; where Early is an early signal with favorable (best case) tolerance stack up, such that, early=tLZ(min); and Late is a late signal with unfavorable (worst case) tolerance stack up, such that, late=tDQSCK(max)−½tT.
As clock periods become ever shorter as clocking frequencies increase, the margin correspondingly decreases. As shown in Table 2, the margin is 2.388 nsec for a 7.5 nsec clock period and 1.938 nsec for a 6 nsec clock period.
TABLE 2Timing Margin for 4th to 1th Socket Readwith 7.5 and 6 nsec clock periodsclocktLZ(min)tDQSCK(max)½ tTmaxslewearlylatemargin7.50.750.750.1380.750.6122.38860.60.60.1380.60.4621.938
(All units are in nsec, and all definitions are the same as the previous table.)
Once again, provided the electrical line length (in time) is short enough, conflicting data transfers associated with different DQS preamble signals will not occur. But some conventional memory modules already cannot accommodate a 7.5 nsec period clock because their electrical line length between the 4th and 1st socket (in terms of the time it takes to propagate signals) exceeds 2.388 nsec.
As such, the memory device arts are desirous of memories capable of accommodating faster clocking frequencies without having to facilitate redesigned electrical line lengths.